Semiconductor devices and methods of fabricating the same

ABSTRACT

A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. Non-Provisional Pat. Application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2021-0105272, filed onAug. 10, 2021, in the Korean Intellectual Property Office, the entirecontents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present disclosure relates to semiconductor devices, and inparticular, semiconductor devices including field effect transistors andmethods of fabricating the same.

A semiconductor device may include an integrated circuit comprisingmetal-oxide-semiconductor field-effect transistors (MOSFETs). To meet anincreasing demand for a semiconductor device with a small pattern sizeand a reduced design rule, the MOSFETs are being aggressively scaleddown. The scale-down of the MOSFETs may lead to deterioration inoperational properties of the semiconductor device. Accordingly, avariety of studies are being conducted to overcome technical limitationsassociated with the scale-down of the semiconductor device and torealize high performance semiconductor devices.

SUMMARY

One embodiment of the present disclosure provides a semiconductor devicewith improved electrical characteristics and reliability and a method offabricating the same.

According to one embodiment of the present disclosure, a semiconductordevice may comprise: an active pattern on a substrate and extending in afirst direction; a plurality of source/drain patterns on the activepattern and spaced apart from each other in the first direction; a gateelectrode between the source/drain patterns that crosses the activepattern and extends in a second direction intersecting the firstdirection; and a plurality of channel patterns stacked on the activepattern and configured to connect two or more of the plurality ofsource/drain patterns to each other. The plurality of channel patternsmay be spaced apart from each other, such as in a directionperpendicular to a plane defined by an upper surface of the substrate.Each of the plurality of channel patterns may include a first portionbetween the gate electrode and the plurality of source/drain patterns,and a plurality of second portions connected to the first portion andoverlapped with the gate electrode in a direction perpendicular to aplane defined by an upper surface of the substrate. Each of theplurality of second portions may be spaced apart from each other in thesecond direction.

According to another embodiment of the present disclosure, asemiconductor device may comprise: an active pattern on a substrate thatextends in a first direction; a plurality of source/drain patterns onthe active pattern and spaced apart from each other in the firstdirection; a gate electrode between the source/drain patterns thatcrosses the active pattern and extends in a second directionintersecting the first direction; a plurality of channel patternsstacked on the active pattern and configured to connect two or more ofthe plurality of source/drain patterns to each other; a gate insulatingpattern between the gate electrode and the plurality of channelpatterns; a plurality of gate spacers extending from a top surface of anuppermost one of the plurality of channel patterns to be on at least aportion of a side surface of the gate electrode; a gate capping patternbetween the gate spacers and on a top surface of the gate electrode; aninterlayer insulating layer on a top surface of one or more of theplurality of source/drain patterns, a side surface of one or more of theplurality of gate spacers, and a top surface of the gate cappingpattern; a plurality of active contacts penetrating the interlayerinsulating layer and connected to respective ones of the plurality ofsource/drain patterns; and a gate contact penetrating the gate cappingpattern and the interlayer insulating layer and connected to the gateelectrode. The plurality of channel patterns may be spaced apart fromeach other, such as in a direction perpendicular to a plane defined byan upper surface of the substrate. Each of the plurality of channelpatterns may include a first portion between the gate electrode and theplurality of source/drain patterns and a plurality of second portionsconnected to the first portion and overlapped with the gate electrode ina direction perpendicular to a plane defined by an upper surface of thesubstrate. The plurality of second portions may be spaced apart fromeach other in the second direction.

According to another embodiment of the present disclosure, asemiconductor device may comprise: a substrate comprising a first cellregion and a second cell region; a plurality of active patterns on eachof the first and second cell regions of the substrate and extending in afirst direction; a first plurality of source/drain patterns on the firstcell region and spaced apart from each other in the first direction; agate electrode between the first plurality of source/drain patterns thatcrosses at least one of the plurality of active patterns and extends ina second direction intersecting the first direction; and a firstplurality of channel patterns stacked on the first cell region andconfigured to connect two or more of the first plurality of source/drainpatterns to each other. The first plurality of channel patterns may bespaced apart from each other, such as in a direction in a directionperpendicular to a plane defined by an upper surface of the substrate.Each of the first plurality of channel patterns may include a firstportion between the gate electrode and the first plurality ofsource/drain patterns and a plurality of second portions connected tothe first portion and overlapped with the gate electrode in a directionperpendicular to a plane defined by an upper surface of the substrate.The plurality of second portions may be spaced apart from each other inthe second direction.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view illustrating a semiconductor device according toan embodiment of the present disclosure.

FIG. 1B is a plan view illustrating one of a plurality of channelpatterns of a semiconductor device according to an embodiment of thepresent disclosure and corresponding to a portion ‘I’ of FIG. 1A.

FIGS. 2A, 2B, 2C, and 2D are sectional views, which are respectivelytaken along lines A-A', B-B', C-C', and D-D′ of FIG. 1A to illustrate asemiconductor device according to an embodiment of the presentdisclosure.

FIGS. 3 and 4 are sectional views, each of which is respectively takenalong the line D-D′ of FIG. 1A to illustrate a semiconductor deviceaccording to an embodiment of the present disclosure.

FIGS. 5A, 6A, 10A, 12A, and 13A are plan views illustrating a method offabricating a semiconductor device according to an embodiment of thepresent disclosure and corresponding to the portion ‘I’ of FIG. 1A.

FIGS. 5B, 6B, 11A, 12B, 13B, and 14A are sectional views, each of whichis taken along a line A-A' of a corresponding plan view, to illustrate amethod of fabricating a semiconductor device according to an embodimentof the present disclosure.

FIG. 10B is a sectional view, which is taken along a line B-B' of acorresponding plan view, to illustrate a method of fabricating asemiconductor device according to an embodiment of the presentdisclosure.

FIG. 10C is a sectional view, which is taken along a line C-C' of acorresponding plan view, to illustrate a method of fabricating asemiconductor device according to an embodiment of the presentdisclosure.

FIGS. 5C, 6C, 7, 8, 9, 10D, 11B, 12C, and 14B are sectional views, eachof which is taken along a line D-D' of a corresponding plan view, toillustrate a method of fabricating a semiconductor device according toan embodiment of the present disclosure.

DETAILED DESCRIPTION

Example embodiments of the present disclosure will now be described morefully with reference to the accompanying drawings, in which exampleembodiments are shown.

FIG. 1A is a plan view illustrating a semiconductor device according toan embodiment of the present disclosure. FIG. 1B is a plan viewillustrating one of channel patterns of a semiconductor device accordingto an embodiment of the present disclosure and corresponding to aportion ‘I’ of FIG. 1A. FIGS. 2A, 2B, 2C, and 2D are sectional views,which are respectively taken along lines A-A′, B-B', C-C', and D-D' ofFIG. 1A, to illustrate a semiconductor device according to an embodimentof the present disclosure.

Referring to FIGS. 1A, 1B, 2A, 2B, 2C, and 2D, a substrate 100 includingat least one active pattern AP may be provided. The substrate 100 may bea semiconductor substrate which is formed of or includes at least oneof, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe),or compound semiconductor materials. In one embodiment, the substrate100 may be a silicon wafer. A top surface of the substrate 100 may beparallel to a first direction D1 and a second direction D2 and may beperpendicular to a third direction D3. The first direction D1, thesecond direction D2, and the third direction D3 may be orthogonal toeach other.

The active pattern AP may include a plurality of active patterns APwhich extend in the first direction D1 and are spaced apart from eachother in the second direction D2. One of the active patterns AP may beprovided on a first cell region PR, and another of the active patternsAP may be provided on a second cell region NR. The first and second cellregions PR and NR may be regions in which a standard cell constituting alogic circuit is provided. The transistors provided on the first andsecond cell regions PR and NR may be logic transistors. As an example,the first cell region PR may be a region in which PMOS field effecttransistors are provided, and the second cell region NR may be a regionin which NMOS field effect transistors are provided. The descriptionthat follows will refer to an example in which a single active patternAP is provided on the first cell region PR, for convenience indescription, but the remaining active patterns AP may be configured tohave substantially the same features as those described below.

A top surface of the active pattern AP may have at least one recessedportion RC. That is, a portion of the top surface of the active patternAP may be recessed toward a bottom surface of the substrate 100. In oneembodiment, a width WRC of the recessed portion RC in the seconddirection D2 may range from about five (5) nanometers (nm) to aboutforty (40) nm. As an example, the width WRC of the recessed portion RCin the second direction D2 may range from about 10 nm to 30 nm. A widthof the recessed portion RC in the first direction D1 may besubstantially equal to a width of a gate electrode GE in the firstdirection D1. The width of the recessed portion RC in the firstdirection D1 may be defined as the largest width of the recessed portionRC in the first direction D1 or an upper width of the recessed portionRC in the first direction D1. The width WRC of the recessed portion RCin the second direction D2 may be defined as the largest width of therecessed portion RC in the second direction D2 or an upper width of therecessed portion RC in the second direction D2.

Referring to FIG. 2A, a bottom surface RCb of the recessed portion RCmay be located at a level lower than a topmost surface 100 tm of thesubstrate 100 where an upper layer of the substrate may serve as a basereference layer, but the present disclosure is not limited to thisexample. The topmost surface 100 tm of the substrate 100 may correspondto the topmost surface of the active pattern AP. In one embodiment, thebottom surface RCb of the recessed portion RC may be located at a levellower than a top surface STt of a device isolation layer ST where anupper layer of the substrate may serve as a base reference layer, butthe present disclosure is not limited to this example. In oneembodiment, the bottom surface RCb of the recessed portion RC may belocated at a level which is lower than the topmost surface 100 tm of thesubstrate 100 and higher than the top surface STt of the deviceisolation layer ST, where an upper level of the substrate may serve as abase reference layer.

The device isolation layer ST may be provided on the substrate 100 todefine the active pattern AP. The device isolation layer ST may be on,and at least partially cover, at least a portion of side surfaces of theactive pattern AP and may expose at least a portion of the top surfaceof the active pattern AP. The device isolation layer ST may be formed ofor include at least one of, for example, silicon oxide, silicon nitride,or silicon oxynitride. The active pattern AP may correspond to an upperportion of the substrate 100 enclosed by the device isolation layer ST.

A plurality of source/drain patterns SD may be on the active pattern APof the substrate 100 and may extend in the second direction D2. Theplurality of source/drain patterns SD may be spaced apart from eachother in the first direction D1. Each of the plurality of source/drainpatterns SD may be in contact with one or more pf a plurality of channelpatterns CH. The plurality of source/drain patterns SD which areprovided on the first cell region PR will be referred to as a ‘firstplurality of source/drain patterns’, and the source/drain patterns SDwhich are provided on the second cell region NR will be referred to as a‘second plurality of source/drain patterns’.

The plurality of source/drain patterns SD may be epitaxial patterns,which are formed using the substrate 100 and the channel patterns CH asa seed layer. The plurality of source/drain patterns SD may be formed ofor include at least one of doped semiconductor materials. The pluralityof source/drain patterns SD may be formed of or include at least one of,for example, silicon (Si), silicon germanium (SiGe), or silicon carbide(SiC). The plurality of source/drain patterns SD may be configured toexert a tensile strain or compressive strain on the channel patterns CH.

Referring to FIGS. 2B and 2D, at least a portion of the plurality ofsource/drain patterns SD may be buried in the active pattern AP. Abottom surface SDb of each of the plurality of source/drain patterns SDmay be located at a level lower than the top surface STt of the deviceisolation layer ST, where an upper level of the substrate may serve as abase reference layer. The bottom surface SDb of each of the plurality ofsource/drain patterns SD may be in contact with at least a portion ofthe top surface of the active pattern AP, and in one embodiment, anentirety of the bottom surface SDb of each of the plurality ofsource/drain patterns SD may be in contact with an entirety of the topsurface of the active pattern AP. One or more of the plurality ofsource/drain patterns SD may have side surfaces which are located on thetop surface STt of the device isolation layer ST, each of which extendsfrom a corresponding one of the side surfaces of the active pattern APin the second direction D2.

The gate electrodes GE may extend in the second direction D2 to crossthe active pattern AP of the substrate 100. Each of the gate electrodesGE may be between a corresponding pair of the plurality of source/drainpatterns SD. Each of the gate electrodes GE may be spaced apart fromeach of the plurality of source/drain patterns SD in the first directionD1. The description that follows will refer to an example in which apair of the source/drain patterns SD and one gate electrode GEtherebetween are provided, for convenience in description, but theremaining gate electrodes GE and the remaining source/drain patterns SDmay be configured to have substantially the same features as those inthe example to be described below.

The gate electrode GE may be on, and at least partially cover, the topsurface STt of the device isolation layer ST, a top surface of theactive pattern AP, and top and bottom surfaces of the channel patternsCH. The gate electrode GE may be formed of or include at least one of,for example, doped semiconductor materials, conductive metal nitrides,and/or metallic materials. More specifically, the gate electrode GE mayinclude a plurality of different metal patterns. The metal patterns mayhave electric resistances different from each other. By adjusting athickness and composition of each of the metal patterns, it may bepossible to realize a transistor having a desired threshold voltage.

The plurality of channel patterns CH may be on the active pattern AP ofthe substrate 100. The plurality of channel patterns CH may be stackedin the third direction D3 perpendicular to the top surface of thesubstrate 100, and in one embodiment, the plurality of channel patternsCH may be sequentially stacked. Each of the plurality of channelpatterns CH may extend in the first direction D1 and may be configuredto connect two or more of the plurality of source/drain patterns SD toeach other. The plurality of channel patterns CH may be spaced apartfrom each other in the third direction D3. The gate electrode GE (orsecond gate spacers GS2 to be described below) may be interposed betweentwo or more of the plurality of channel patterns CH, which are spacedapart from each other in the third direction D3. More specifically, thesecond gate spacers GS2 may be interposed between two or more of theplurality of channel patterns CH, which correspond to a first portion P1to be described below, and the gate electrode GE may be interposedbetween two or more of the plurality of channel patterns CH, whichcorrespond to a plurality of second portions P2 to be described below.Ones of the plurality of channel patterns CH which are provided on thefirst cell region PR will be referred to as a ‘first plurality ofchannel patterns’, and ones of the plurality of channel patterns CHwhich are provided on the second cell region NR will be referred to as a‘second plurality of channel patterns’.

In one embodiment, the gate electrode GE, the plurality of channelpatterns CH, and the plurality of source/drain patterns SD mayconstitute a logic transistor, and the logic transistor may be athree-dimensional field effect transistor (e.g., a gate-all-around (GAA)type transistor), in which the gate electrode GE is provided tothree-dimensionally surround the channel patterns CH.

Referring to FIGS. 1A and 1B, each of the plurality of channel patternsCH may include a first portion P1, which is between the gate electrodeGE and the plurality of source/drain patterns SD, and a plurality of thesecond portions P2, which are connected to the first portion P1 and arevertically overlapped (i.e., overlapped in a direction perpendicular toa plane defined by an upper surface of the substrate) with the gateelectrode GE in the third direction D3.

The first portion P1 may be in contact with one of the plurality ofsource/drain patterns SD. The first portion P1 may extend in the seconddirection D2 and may be connected to each of the plurality of secondportions P2. Each of the plurality of second portions P2 may be spacedapart from the plurality of source/drain patterns SD in the firstdirection D1, with the first portion P1 interposed therebetween. Theplurality of second portions P2 may be spaced apart from each other, inthe second direction D2, with the recessed portion RC interposedtherebetween, when viewed in a plan view. When viewed in the sectionalview of FIG. 2A, spaces between the second portions P2 may be at leastpartially filled with the gate electrode GE.

In one embodiment, the recessed portion RC may include a plurality ofrecessed portions RC. The recessed portions RC may be spaced apart fromeach other, in the second direction D2, with a portion of the activepattern AP interposed therebetween. FIGS. 1A and 1B illustrate anexample, in which two recessed portions RC and three second portions P2are provided, but the number of the recessed portions RC and the numberof the second portions P2 are not limited to this example.

In one embodiment, lengths LP2 of the plurality of second portions P2 inthe second direction D2 may be different from each other. The length LP2of each of the plurality of second portions P2 in the second directionD2 may be smaller than a length LP1 of the first portion P1 in thesecond direction D2. The length LP2 of each of the plurality of secondportions P2 in the second direction D2 may be smaller than a length LSDof each of the plurality of source/drain patterns SD in the seconddirection D2. In one embodiment, the length LP1 of the first portion P1in the second direction D2 may be smaller than the length LSD of each ofthe source/drain patterns SD in the second direction D2.

A gate insulating pattern GI may be provided between the active patternAP and the gate electrode GE and between each of the channel patterns CHand the gate electrode GE. A plurality of first gate spacers GS1 and aplurality of second gate spacers GS2 may be provided to be on, and atleast partially cover, side surfaces of the gate electrodes GE. A gatecapping pattern GP may be on, and at least partially cover, the topmostsurface of the gate electrode GE. A structure including the gateelectrode GE, the gate insulating pattern GI, the first and second gatespacers GS1 and GS2, and the gate capping pattern GP will be referred toas a gate structure.

The gate insulating pattern GI may extend along a bottom surface of thegate electrode GE and may be interposed between the gate electrode GEand the device isolation layer ST. In other words, the gate insulatingpattern GI may extend in the second direction D2 from a top surface ofthe active pattern AP toward a top surface of the device isolation layerST.

Referring to FIG. 2A, the gate insulating pattern GI may be interposedbetween each of the channel patterns CH and the gate electrode GE. Morespecifically, the gate insulating pattern GI may be provided to cover orface at least a portion of top, bottom, and/or side surfaces of theplurality of second portions P2 of each of the plurality of channelpatterns CH. The second portions P2 of each of the channel patterns CHmay be spaced apart from the gate electrode GE with the gate insulatingpattern GI interposed therebetween.

Referring to FIG. 2D, the gate insulating pattern GI may be interposedbetween the channel patterns CH and the gate electrode GE and betweenthe active pattern AP and the gate electrode GE and may extend intoregions between the gate electrode GE and the first gate spacers GS1 andbetween the gate electrode GE and the second gate spacers GS2. Thetopmost surface of the gate insulating pattern GI may be substantiallycoplanar with the topmost surface of the gate electrode GE. The gateelectrode GE may be spaced apart from the first and second gate spacersGS1 and GS2 with the gate insulating pattern GI interposed therebetween.

The gate insulating pattern GI may be formed of or include at least oneof, for example, silicon oxide, silicon nitride, silicon oxynitride, orhigh-k dielectric materials. The high-k dielectric materials may bematerials (e.g., hafnium oxide (HfO), aluminum oxide (A1O), or tantalumoxide (TaO)) having higher dielectric constants than silicon oxide andsilicon nitride.

Referring to FIG. 2D, the plurality of first gate spacers GS1 may extendfrom a top surface of the uppermost one of the channel patterns CH inthe third direction D3 to cover at least a portion of the side surfaceof the gate electrode GE, and the plurality of second gate spacers GS2may be between the channel patterns CH and between a lowermost one ofthe channel patterns CH and the active pattern AP to cover anotherportion of the side surface of the gate electrode GE. Each of the firstand second gate spacers GS1 and GS2 may extend along the side surface ofthe gate electrode GE or in the second direction D2. A top surface ofeach of the first gate spacers GS1 may be located at a level higher thanthe topmost surface of the gate electrode GE and may be substantiallycoplanar with a top surface of the gate capping pattern GP. An adjacentpair of the first gate spacers GS1 may be spaced apart from each other,in the first direction D1, with the gate electrode GE and the gatecapping pattern GP interposed therebetween. Each of the second gatespacers GS2 may be provided between each of the plurality ofsource/drain patterns SD and the gate electrode GE. The plurality ofsecond gate spacers GS2 may be in contact with the source/drain patternsSD. In one embodiment, the second gate spacers GS2 may be overlappedwith the first gate spacers GS1 in the third direction D3.

Referring to FIG. 2C, the plurality of second gate spacers GS2 may beprovided between the channel patterns CH, which are spaced apart fromeach other in the third direction D3. The second gate spacers GS2 may bein contact with the first portion P1 of each of the channel patterns CH.

Each of the first and second gate spacers GS1 and GS2 and the gatecapping pattern GP may be formed of or include at least one of, forexample, silicon oxide, silicon nitride, or silicon oxynitride. The gatecapping pattern GP may be formed of or include, for example, siliconnitride.

A first interlayer insulating layer 110 may be provided to at leastpartially cover the top surface STt of the device isolation layer ST,top and side surfaces of the plurality of source/drain patterns SD, sidesurfaces of the plurality of channel patterns CH, and side surfaces ofthe first plurality of gate spacers GS1. A top surface of the firstinterlayer insulating layer 110 may be substantially coplanar with thetop surface of the gate capping pattern GP and the top surfaces of thefirst gate spacers GS1. A second interlayer insulating layer 120 may beon the first interlayer insulating layer 110 to cover at least a portionof the top surface of the gate capping pattern GP and the top surfacesof the first plurality of gate spacers GS1. In one embodiment, the firstand second interlayer insulating layers 110 and 120 may be formed of orinclude silicon oxide.

Active contacts AC may be provided to penetrate the first and secondinterlayer insulating layers 110 and 120 and may be electricallyconnected to the source/drain patterns SD, respectively. A pair of theactive contacts AC may be respectively provided at both sides of thegate electrode GE. When viewed in a plan view, each of the activecontacts AC may be a line- or bar-shaped pattern which is extended inthe second direction D2.

Each of the active contacts AC may include a conductive pattern FM and abarrier pattern BM enclosing the conductive pattern FM. For example, theconductive pattern FM may be formed of or include at least one ofmetallic materials (e.g., aluminum, copper, tungsten, molybdenum, andcobalt). The barrier pattern BM may cover at least a portion of side andbottom surfaces of the conductive pattern FM. In an embodiment, thebarrier pattern BM may include a metal layer and a metal nitride layer.The metal layer may be formed of or include at least one of titanium,tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layermay be formed of or include at least one of titanium nitride (TiN),tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN),cobalt nitride (CoN), or platinum nitride (PtN).

A plurality of active contacts AC may be self-aligned contacts. In otherwords, the active contacts AC may be formed in a self-aligned mannerusing the gate capping pattern GP and the first gate spacer GS1. Forexample, the active contacts AC may be on at least a portion of the sidesurfaces of the first gate spacers GS1. In one embodiment, each of theactive contacts AC may cover at least a portion of the top surface ofthe gate capping pattern GP.

A silicide pattern SC may be provided between each of the plurality ofactive contacts AC and each of the source/drain patterns SD. Each of theactive contacts AC may be electrically connected to a corresponding oneof the source/drain patterns SD through the silicide pattern SC. Thesilicide pattern SC may be formed of or include at least one ofmetal-silicide materials. For example, the silicide pattern SC may beformed of or include at least one of titanium silicide, tantalumsilicide, tungsten silicide, nickel silicide, or cobalt silicide.

A gate contact GC may penetrate the second interlayer insulating layer120 and the gate capping pattern GP and may be electrically connected tothe gate electrode GE. In one embodiment, the gate contact GC may be onthe device isolation layer ST between the first and second cell regionsPR and NR. When viewed in a plan view, the gate contact GC may be aline- or bar-shaped pattern extending in the first direction D1. Thegate contact GC may include the conductive pattern FM and the barrierpattern BM enclosing the conductive pattern FM, similar to the activecontacts AC.

A third interlayer insulating layer 130 may be on the second interlayerinsulating layer 120. First interconnection lines M1, a first via V1,and a second via V2 may be provided in the third interlayer insulatinglayer 130. The first and second vias V1 and V2 may be below the firstinterconnection lines M1. The first interconnection lines M1 may extendin the first direction D1. The first interconnection lines M1 may bearranged in the first direction D1 or the second direction D2. The firstvia V1 may be between one of the first interconnection lines M1 and oneof the active contacts AC to electrically connect them to each other.The second via V2 may be between one of the first interconnection linesM1 and the gate contact GC to electrically connect them to each other.

The first interconnection lines M1 and the first or second via V1 or V2may be connected to each other, thereby forming a single conductivestructure. For example, the first interconnection lines M1 and the firstor second via V1 or V2 may be formed through the same process. The firstinterconnection lines M1 and the first or second via V1 or V2 may form asingle conductive structure which is patterned by a dual damasceneprocess. In one embodiment, some metal layers (e.g., M2, M3, M4, and soforth) may be additionally stacked on the third interlayer insulatinglayer 130.

FIGS. 3 and 4 are sectional views, each of which is respectively takenalong the line D-D' of FIG. 1A to illustrate a semiconductor deviceaccording to an embodiment of the present disclosure. For concisedescription, a previously-described element may be identified by thesame reference number without repeating an overlapping descriptionthereof.

Referring to FIGS. 1A and 3 , the plurality of second gate spacers GS2of FIG. 2D may not be provided. The gate electrodes GE may extend in thefirst direction D1 between the channel patterns CH and may be spacedapart from each of the plurality of source/drain patterns SD by only thegate insulating pattern GI interposed therebetween. For example, thegate electrode GE may be provided in place of the second gate spacersGS2 of FIG. 2C. In other words, at least a portion of the gate electrodeGE may overlap the first portion P1 of each of the channel patterns CHin the third direction D3.

Referring to FIGS. 1A and 4 , the number of the channel patterns CH,which are spaced apart from each other in the third direction D3, may begreater than or equal to four. However, the number of the stackedchannel patterns CH is not limited to the examples of FIGS. 2D and 4 ,and in one embodiment, the number of the channel patterns CH stacked inthe third direction D3 may be greater than or equal to two.

FIGS. 5A, 6A, 10A, 12A, and 13A are plan views illustrating a method offabricating a semiconductor device according to one embodiment of thepresent disclosure and corresponding to the portion ‘I’ of FIG. 1A.FIGS. 5B, 6B, 11A, 12B, 13B, and 14A are sectional views, each of whichis taken along a line A-A′ of a corresponding plan view, to illustrate amethod of fabricating a semiconductor device according to one embodimentof the present disclosure. FIG. 10B is a sectional view, which is takenalong a line B-B' of a corresponding plan view, to illustrate a methodof fabricating a semiconductor device according to one embodiment of thepresent disclosure. FIG. 10C is a sectional view, which is taken along aline C-C' of a corresponding plan view, to illustrate a method offabricating a semiconductor device according to one embodiment of thepresent disclosure. FIGS. 5C, 6C, 7, 8, 9, 10D, 11B, 12C, and 14B aresectional views, each of which is taken along a line D-D' of acorresponding plan view, to illustrate a method of fabricating asemiconductor device according to one embodiment of the presentdisclosure.

Hereinafter, the fabrication method will be described in more detailwith reference to FIGS. 5A to 14B.

Referring to FIGS. 5A, 5B, and 5C, the substrate 100 may be provided inthe form of a plate extended in the first and second directions D1 andD2, and in one embodiment, the substrate 100 may be formed of or includea semiconductor material. First and second semiconductor layers may bealternately and repeatedly stacked on the substrate 100. The secondsemiconductor layer may be formed of or include a material having anetch selectivity with respect to the first semiconductor layer. Forexample, the first and second semiconductor layers may be formed of orinclude at least one of silicon (Si), germanium (Ge), or silicongermanium (SiGe), but the materials for the first and secondsemiconductor layers may be different from each other. As an example,the first semiconductor layers may be formed of or include silicon (Si),and the second semiconductor layers may be formed of or include silicongermanium (SiGe).

A patterning process may be performed on the substrate and the first andsecond semiconductor layers. For example, the patterning process may beperformed to form a trench defining the active pattern AP. The deviceisolation layer ST may be formed in the trench. The device isolationlayer ST may be formed of or include, for example, silicon oxide. Thedevice isolation layer ST may be recessed such that an upper portion ofthe active pattern AP protrudes above the device isolation layer ST.

During the patterning process, the first and second semiconductor layersmay be partially removed to form first semiconductor patterns SP1 andsecond semiconductor patterns SP2, respectively. The first and secondsemiconductor patterns SP1 and SP2 may be alternately and repeatedlystacked on the active pattern AP.

A buffer layer BF may be formed on a portion of the active pattern APprotruding above the device isolation layer ST. The buffer layer BF maycover at least a portion of side surfaces of the first and secondsemiconductor patterns SP1 and SP2 and at least a portion of a topsurface of the uppermost one of the first semiconductor patterns SP1.Furthermore, the buffer layer BF may extend to cover at least a portionof the top surface of the device isolation layer ST. The buffer layer BFmay be formed of or include, for example, silicon oxide.

Referring to FIGS. 6A, 6B, and 6C, at least one sacrificial pattern PPmay be formed to cross the active pattern AP. The at least onesacrificial pattern PP may be formed to have a line or bar shapeextending in the second direction D2. The at least one sacrificialpattern PP may include a plurality of sacrificial patterns PP. Theplurality of sacrificial patterns PP may be spaced apart from each otherin the first direction D1. One of the sacrificial patterns PP will bedescribed below, but the remaining ones of the sacrificial patterns PPmay also have substantially the same features as described below.

The formation of the sacrificial pattern PP may include forming asacrificial layer on the substrate 100, forming a hard mask pattern MPon the sacrificial layer, and patterning the sacrificial layer and thebuffer layer BF using the hard mask pattern MP as an etch mask. Thesacrificial layer may be formed of or include, for example, polysilicon. The hard mask pattern MP may be formed of or include, forexample, silicon nitride.

Referring to FIG. 7 , a first gate spacer layer GSL1 may be formed on atleast a portion of a top surface of the uppermost one of the firstsemiconductor patterns SP1, at least a portion of a top surface of thehard mask pattern MP, and at least a portion of side surfaces of thehard mask pattern MP, the sacrificial pattern PP, and the buffer layerBF. The first gate spacer layer GSL1 may be formed of or include, forexample, silicon nitride.

Referring to FIGS. 7 and 8 , portions of the first gate spacer layerGSL1, which covers at least a portion of the top surface of theuppermost one of the first semiconductor patterns SP1 and at least aportion of the top surface of the hard mask pattern MP, may be removedto form the first gate spacers GS1 covering opposite side surfaces ofthe sacrificial pattern PP.

The active pattern AP may be partially recessed to form a plurality offirst recessed portions RC1. The first recessed portions RC1 may beformed at both sides of the sacrificial pattern PP. The plurality offirst recessed portions RC1 may be formed by etching an upper portion ofthe active pattern AP using the hard mask pattern MP and the first gatespacers GS1 as an etch mask.

Referring to FIG. 9 , a plurality of second recessed portions RC2 may berespectively formed by recessing the second semiconductor patterns SP2,which are exposed through the first recessed portions RC1, in the firstdirection D1. The first semiconductor patterns SP1, which are exposedthrough the first recessed portions RC1, may not be removed during theformation of the second recessed portions RC2.

Referring to FIGS. 10A, 10B, 10C, and 10D, a plurality of second gatespacers GS2 may be formed to completely or partially fill the secondrecessed portions RC2. The plurality of second gate spacers GS2 may beformed of or include, for example, silicon nitride. The formation of theplurality of second gate spacers GS2 may include forming a second gatespacer layer to completely or partially fill the second recessedportions RC2 and at least a portion of the first recessed portions RC1and removing a portion of the second gate spacer layer formed in thefirst recessed portions RC1. Referring to FIG. 10C, the plurality ofsecond gate spacers GS2 may be formed to completely or partially fillspaces which are provided between the first semiconductor patterns SP1and between the sacrificial pattern PP and the plurality of source/drainpatterns SD.

Next, the plurality of source/drain patterns SD may be formed to atleast partially fill the first recessed portions RC1, which are formedin the upper portion of the active pattern AP. The source/drain patternsSD may be respectively formed at both sides of the sacrificial patternPP. The top surface of each of the plurality of source/drain patterns SDis illustrated to be substantially coplanar with the top surface of theuppermost one of the first semiconductor patterns SP1, but the presentdisclosure is not limited to this example. For example, each of theplurality of source/drain patterns SD may be formed such that its topsurface is located at a level higher than the top surface of theuppermost one of the first semiconductor patterns SP1. Referring to FIG.10B, the bottom surface SDb of each of the plurality of source/drainpatterns SD may be located at a level lower than the top surface STt ofthe device isolation layer ST, where an upper level of the substrate mayserve as a base reference layer.

The plurality of source/drain patterns SD may be formed by a selectiveepitaxial growth process using the top surface of the active pattern AP,which is exposed through the first recessed portions RC1, and inner sidesurfaces of the first recessed portions RC1 as a seed layer. As anexample, during the selective epitaxial growth process, the plurality ofsource/drain patterns SD may be doped with impurities in situ. Asanother example, impurities may be injected into the source/drainpatterns SD, after the formation of the source/drain patterns SD.

Referring to FIGS. 11A and 11B, a first interlayer insulating layer 110may be formed to at least partially cover side surfaces of the firstplurality of gate spacers GS1, top surfaces of the plurality ofsource/drain patterns SD, and a portion of the top surface of the activepattern AP which is not covered with the sacrificial pattern PP. Thehard mask pattern MP on the sacrificial pattern PP may be removedthrough a planarization process. In one embodiment, the planarizationprocess may be an etch-back process or a chemical mechanical polishing(CMP) process. The first interlayer insulating layer 110 may also beremoved during the planarization process. The top surface of the firstinterlayer insulating layer 110 may be substantially coplanar with topsurfaces of the first gate spacers GS1 and a top surface of thesacrificial pattern PP.

Referring to FIGS. 12A, 12B, and 12C in conjunction with FIGS. 10A, 11A,and 11C, the sacrificial pattern PP on the active pattern AP may beremoved. An empty space, which is formed between the first gate spacersGS1 by the removal of the sacrificial pattern PP, may be referred to asa first empty space ES1. In one embodiment, the buffer layer BF belowthe sacrificial pattern PP may also be removed during the process ofremoving the sacrificial pattern PP. As a result of the removal of thesacrificial pattern PP, side surfaces of the first gate spacers GS1 anda top surface of the uppermost one of the first semiconductor patternsSP1 may be exposed to the outside.

Referring to FIGS. 13A and 13B, at least one third recessed portion RC3may be formed by performing a patterning process on the first and secondsemiconductor patterns SP1 and SP2, which are exposed by the first emptyspace ES1. The bottom surface RCb of the third recessed portion RC3 maybe located at a level lower than a topmost surface 100 tm of thesubstrate 100, where an upper level of the substrate may serve as a basereference layer. In the first empty space ES1, each of the first andsecond semiconductor patterns SP1 and SP2 may include portions which arespaced apart from each other in the second direction D2. The thirdrecessed portion RC3 may correspond to the recessed portion RC in FIGS.1A, 1B, and 2A.

Referring to FIGS. 14A and 14B, the second semiconductor patterns SP2may be selectively removed. Empty spaces, which are formed between thefirst semiconductor patterns SP1 by the selectively removal of thesecond semiconductor patterns SP2, may be referred to as second emptyspaces ES2. As a result of the removal of the second semiconductorpatterns SP2, side surfaces of the second gate spacers GS2 and top andbottom surfaces of the first semiconductor patterns SP1 may be exposedto the outside.

Referring to FIGS. 14A and 14B in conjunction with FIGS. 1A, 1B, 2A, 2B,2C, and 2D, the gate electrode GE may be formed to completely orpartially fill the first and second empty spaces ES1 and ES2. Before theformation of the gate electrode GE, the gate insulating pattern GI maybe formed on, and conform to, at least a portion of side, top, andbottom surfaces of the first and second empty spaces ES1 and ES2. Thefirst semiconductor patterns SP1 may be referred to as the channelpatterns CH.

Next, the gate capping pattern GP may be formed on the gate electrodeGE. The formation of the gate capping pattern GP may include recessing aportion of the gate electrode GE at least partially filling the firstempty space ES1, forming a capping layer to at least partially fill therecessed space of the gate electrode GE, and performing a planarizationprocess to remove a portion of the capping layer. The gate cappingpattern GP may be formed of or include, for example, silicon nitride.The top surface of the gate capping pattern GP may be substantiallycoplanar with the top surfaces of the first gate spacers GS1.

The second interlayer insulating layer 120 may be formed on the topsurface of the first interlayer insulating layer 110 and on the topsurface of the gate capping pattern GP. The active contacts AC may beformed to penetrate the first and second interlayer insulating layers110 and 120 and may be electrically connected to the source/drainpatterns SD. The gate contacts GC may be provided to penetrate thesecond interlayer insulating layer 120 and the gate capping pattern GPand may be electrically connected to the gate electrodes GE.

The third interlayer insulating layer 130 may be formed on the activecontacts AC and the gate contact GC. A first metal layer may be formedin the third interlayer insulating layer 130, and in one embodiment, thefirst metal layer may include the first interconnection lines M1, thefirst via V1, and the second via V2. Additional metal layers (e.g., M2,M3, M4, and so forth) may be further stacked on the third interlayerinsulating layer 130.

In the case where a plurality of channel patterns, which are verticallyspaced apart (i.e., spaced apart in a direction perpendicular to a planedefined by an upper surface of the substrate) from each other to connectsource/drain patterns to each other, are formed to have an increasedlength in a horizontal direction, various difficulties may occur in afabrication process. For example, in a process of selectively etching asemiconductor layer between the channel patterns, it may be difficult tocompletely remove the semiconductor layer. However, according to anembodiment of the present disclosure, it may be possible to overcomesuch difficulties, to minimize a pitch of the channel patterns, and toimprove electrical characteristics and reliability of the semiconductordevice.

While example embodiments of the present disclosure have beenparticularly shown and described, it will be understood by one ofordinary skill in the art that variations in form and detail may be madetherein without departing from the spirit and scope of the attachedclaims.

What is claimed is:
 1. A semiconductor device, comprising: an activepattern on a substrate and extending in a first direction; a pluralityof source/drain patterns on the active pattern and spaced apart fromeach other in the first direction; a gate electrode between theplurality of source/drain patterns that crosses the active pattern andextends in a second direction intersecting the first direction; and aplurality of channel patterns stacked on the active pattern andconfigured to connect two or more of the plurality of source/drainpatterns to each other, wherein each of the plurality of channelpatterns is spaced apart from another one of the plurality of channelpatterns, wherein each of the plurality of channel patterns comprises: afirst portion between the gate electrode and the plurality ofsource/drain patterns; and a plurality of second portions connected tothe first portion and overlapped with the gate electrode in a directionperpendicular to a plane defined by an upper surface of the substrate,and wherein each of the plurality of second portions are spaced apartfrom another one of the plurality of second portions in the seconddirection.
 2. The semiconductor device of claim 1, wherein a top surfaceof the active pattern has a first recessed portion between two of theplurality of second portions.
 3. The semiconductor device of claim 2,wherein a width of the first recessed portion in the second directionranges from about five (5) nanometers (nm) to about forty (40) nm. 4.The semiconductor device of claim 2, wherein a width of the firstrecessed portion in the first direction is equal to a width of the gateelectrode in the first direction.
 5. The semiconductor device of claim2, further comprising a device isolation layer on the substrate todefine the active pattern, wherein a bottom surface of the firstrecessed portion is located at a level lower than a top surface of thedevice isolation layer, where an upper layer of the substrate serves asa base reference layer.
 6. The semiconductor device of claim 2, furthercomprising a second recessed portion between two of the plurality ofsecond portions, wherein the first recessed portion and the secondrecessed portion are spaced apart from each other in the seconddirection.
 7. The semiconductor device of claim 1, wherein a length ofat least one of the plurality of second portions in the second directionis smaller than a length of the first portion in the second direction.8. The semiconductor device of claim 1, wherein a length of the firstportion in the second direction is smaller than a length of each of theplurality of source/drain patterns in the second direction.
 9. Thesemiconductor device of claim 1, further comprising a device isolationlayer on the substrate to define the active pattern, wherein a bottomsurface of each of the plurality of source/drain patterns is located ata level lower than a top surface of the device isolation layer, where anupper layer of the substrate serves as a base reference layer; andwherein the gate electrode is on at least a portion of a top surface ofthe device isolation layer, at least a portion of a top surface of theactive pattern, and at least a portion of top and bottom surfaces of theplurality of channel patterns.
 10. The semiconductor device of claim 1,wherein an entirety of a bottom surface of each of the plurality ofsource/drain patterns is in contact with an entirety of a top surface ofthe active pattern.
 11. The semiconductor device of claim 1, wherein theplurality of channel patterns comprises four or more channel patterns,the semiconductor device further comprising at least one first gatespacer and at least one second gate spacer on a side surface of the gateelectrode, wherein the at least one first gate spacer extends from a topsurface of an uppermost one of the plurality of channel patterns in adirection perpendicular to a plane defined by an upper surface of thesubstrate, and the at least one second gate spacer is between two ormore of the plurality of channel patterns and contacts at least aportion of one of the plurality of channel patterns.
 12. Thesemiconductor device of claim 11, wherein the at least one second gatespacer overlaps the first portion of each of the plurality of channelpatterns in a direction perpendicular to a plane defined by an uppersurface of the substrate.
 13. A semiconductor device, comprising: anactive pattern on a substrate and extending in a first direction; aplurality of source/drain patterns on the active pattern and spacedapart from each other in the first direction; a gate electrode betweenthe plurality of source/drain patterns that crosses the active patternand extends in a second direction intersecting the first direction; aplurality of channel patterns stacked on the active pattern andconfigured to connect two or more of the plurality of source/drainpatterns to each other; a gate insulating pattern between the gateelectrode and the plurality of channel patterns; a plurality of gatespacers extending from a top surface of an uppermost one of theplurality of channel patterns in a direction perpendicular to a planedefined by an upper surface of the substrate to be on at least a portionof a side surface of the gate electrode; a gate capping pattern betweenthe gate spacers and on a top surface of the gate electrode; aninterlayer insulating layer on at least one top surface of one or moreof the plurality of source/drain patterns, at least one side surface ofone or more of the plurality of gate spacers, and a top surface of thegate capping pattern; a plurality of active contacts penetrating theinterlayer insulating layer and connected to two or more of theplurality of source/drain patterns; and a gate contact penetrating thegate capping pattern and the interlayer insulating layer and connectedto the gate electrode, wherein each of the plurality of channel patternsis spaced apart from another one of the plurality of channel patterns,wherein each of the plurality of channel patterns comprises: a firstportion between the gate electrode and the plurality of source/drainpatterns; and a plurality of second portions connected to the firstportion and overlapped with the gate electrode in a directionperpendicular to a plane defined by an upper surface of the substrate,and wherein each of the plurality of second portions are spaced apartfrom another one of the plurality of second portions in the seconddirection.
 14. The semiconductor device of claim 13, wherein the firstportion contacts at least one of the plurality of source/drain patterns.15. The semiconductor device of claim 13, wherein each of the pluralityof second portions is spaced apart from the plurality of source/drainpatterns with the first portion interposed therebetween.
 16. Thesemiconductor device of claim 13, wherein the first portion isoverlapped with the gate spacer in a direction perpendicular to a planedefined by an upper surface of the substrate.
 17. The semiconductordevice of claim 13, wherein at least a portion of the gate electrode,which extends in the first direction between the plurality of channelpatterns, is overlapped with the first portion in a directionperpendicular to a plane defined by an upper surface of the substrate.18. A semiconductor device, comprising: a substrate comprising a firstcell region and a second cell region; a plurality of active patterns oneach of the first and second cell regions of the substrate and extendingin a first direction; a first plurality of source/drain patterns on thefirst cell region and spaced apart from each other in the firstdirection; a gate electrode between the first plurality of source/drainpatterns that crosses at least one of the plurality of active patternsand extends in a second direction intersecting the first direction; anda first plurality of channel patterns stacked on the first cell regionand configured to connect two or more of the first plurality ofsource/drain patterns to each other, wherein each of the first pluralityof channel patterns is spaced apart from another one of the firstplurality of channel patterns, wherein each of the first plurality ofchannel patterns comprises: a first portion between the gate electrodeand the first plurality of source/drain patterns; and a plurality ofsecond portions connected to the first portion and overlapped with thegate electrode in a direction perpendicular to a plane defined by anupper surface of the substrate, and wherein each of the plurality ofsecond portions are spaced apart from another one of the plurality ofsecond portions in the second direction.
 19. The semiconductor device ofclaim 18, further comprising: a second plurality of source/drainpatterns on the second cell region and spaced apart from each other inthe first direction; and a second plurality of channel patterns stackedon the second cell region and configured to connect two or more of thesecond plurality of source/drain patterns to each other, wherein thegate electrode extends from a region between the first plurality ofsource/drain patterns to a region between the second plurality ofsource/drain patterns, wherein the second plurality of source/drainpatterns is spaced apart from the first plurality of source/drainpatterns in the second direction, wherein channel patterns of the secondplurality of channel patterns are spaced apart from each other, whereineach of the second plurality of channel patterns comprises: a firstportion between the gate electrode and the second plurality ofsource/drain patterns; and second portions connected to the firstportion and overlapped with the gate electrode in a directionperpendicular to a plane defined by an upper surface of the substrate,and wherein each of the plurality of second portions is spaced apartfrom another one of the plurality of second portions in the seconddirection.
 20. The semiconductor device of claim 18, wherein a topsurface of each of the plurality of active patterns has a recessedportion between two or more of the plurality of second portions.